This disclosure relates generally to the field of field effect transistor fabrication.
In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of a higher integration density than is currently feasible, field effect transistor (FET) dimensions must be scaled down, as FETs are an important component of many ICs. A Schottky junction source/drain complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) is a viable option for thin-body devices and sub-30 nanometer (nm) gate CMOS technology. Schottky FETs may have relatively low parasitic resistance and gate-to-drain parasitic capacitance, due to the lack of raised source/drain regions, as well as abrupt source/drain junctions. In particular, to fabricate a sub-15 nm FET in silicon-on-insulator (SOI) with good electrostatics and control of the channel region, the semiconductor material in the channel region may need to be very thin, about 7 nm or less. However, achieving a precise thickness at such small dimensions may be difficult; the variation in the thickness of the semiconductor material may be about 2 nm up or down.
The silicon (Si) thickness available for the silicide in source and drain regions may be even less, and with greater variation, because of the Si loss during spacer reactive ion etching (RIE) and pre-silicide cleaning. Insufficient Si thickness raises silicide encroachment and delemination problems during the fully silicided source/drain process, since the metal amount needed is determined by Si thickness in the source/drain. The source and drain semiconductor material may be built up to avoid these issues using epitaxial growth; however, it is difficult to grow an epitaxial layer on a semiconductor layer that is about 5 nm thick or less.